1. Field
Example embodiments relate to semiconductor devices and semiconductor apparatuses including the same. Other example embodiments relate to semiconductor devices having gate patterns, which are disposed on both sides of a body region, and semiconductor apparatuses including the same.
2. Description of the Related Art
Generally, a one transistor (1-T) dynamic random access memory (DRAM), which does not include a capacitor and is implemented using one transistor, has been used. A 1-T DRAM may be manufactured by performing a simple manufacturing operation. A 1-T DRAM may have an increased sensing margin.
FIG. 1 is a front view of a conventional one transistor (1-T) dynamic random access memory (DRAM), which is provided as a comparative example. FIG. 2 is a circuit diagram of the conventional 1-T DRAM illustrated in FIG. 1.
Referring to FIGS. 1 and 2, the conventional 1-T DRAM may be modeled as a bipolar junction transistor (BJT) structure. However, the conventional 1-T DRAM, for example, may have a metal-oxide-semiconductor (MOS) transistor structure. Thus, in the conventional 1-T DRAM, a gate pattern WL 130 may be disposed on a body region including impurity coated regions 140 and 150. Insulation regions 120a and 120b may be on a substrate region 110 and on sides of the impurity coated regions 140 and 150, respectively. A distance between the gate pattern WL 130 and the impurity coated regions 140 and 150 may be substantially small such that the impurity coated regions 140 and 150 are each in close proximity to the gate pattern WL 130. As such, a band-to-band tunneling (BTBT) phenomenon may occur. In the conventional 1-T DRAM, data may be damaged due to a repeated read operation or an increased retention time.